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<title>RDRAND—Read Random Number </title></head>
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<h1>RDRAND—Read Random Number</h1>
<table>
<tr>
<th>Opcode*/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>0F C7 /6</p>
<p>RDRAND r16</p></td>
<td>M</td>
<td>V/V</td>
<td>RDRAND</td>
<td>Read a 16-bit random number and store in the destination register.</td></tr>
<tr>
<td>
<p>0F C7 /6</p>
<p>RDRAND r32</p></td>
<td>M</td>
<td>V/V</td>
<td>RDRAND</td>
<td>Read a 32-bit random number and store in the destination register.</td></tr>
<tr>
<td>
<p>REX.W + 0F C7 /6</p>
<p>RDRAND r64</p></td>
<td>M</td>
<td>V/I</td>
<td>RDRAND</td>
<td>Read a 64-bit random number and store in the destination register.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>M</td>
<td>ModRM:r/m (w)</td>
<td>NA</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Loads a hardware generated random value and store it in the destination register. The size of the random value is determined by the destination register size and operating mode. The Carry Flag indicates whether a random value is available at the time the instruction is executed. CF=1 indicates that the data in the destination is valid. Other-wise CF=0 and the data in the destination operand will be returned as zeros for the specified width. All other flags are forced to 0 in either situation. Software must check the state of CF=1 for determining if a valid random value has been returned, otherwise it is expected to loop and retry execution of RDRAND (see <em>Intel® 64 and IA-32 Archi-tectures Software Developer’s Manual, Volume 1</em>, Section 7.3.17, “Random Number Generator Instructions”).</p>
<p>This instruction is available at all privilege levels.</p>
<p>In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.B permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bit oper-ands. See the summary chart at the beginning of this section for encoding data and limits.</p>
<h2>Operation</h2>
<pre>IF HW_RND_GEN.ready = 1
    THEN
         CASE of
              osize is 64: DEST[63:0] ← HW_RND_GEN.data;
              osize is 32: DEST[31:0] ← HW_RND_GEN.data;
              osize is 16: DEST[15:0] ← HW_RND_GEN.data;
         ESAC
         CF ← 1;
    ELSE
         CASE of
              osize is 64: DEST[63:0] ← 0;
              osize is 32: DEST[31:0] ← 0;
              osize is 16: DEST[15:0] ← 0;
         ESAC
         CF ← 0;
FI
OF, SF, ZF, AF, PF ← 0;</pre>
<h2>Flags Affected</h2>
<p>The CF flag is set according to the result (see the “Operation” section above). The OF, SF, ZF, AF, and PF flags are set to 0.</p>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>RDRAND:</p>
<p> int _rdrand16_step( unsigned short * );</p>
<p>RDRAND:</p>
<p> int _rdrand32_step( unsigned int * );</p>
<p>RDRAND:</p>
<p> int _rdrand64_step( unsigned __int64 *);</p>
<h2>Protected Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#UD</td>
<td>
<p>If the LOCK prefix is used.</p>
<p>If the F2H or F3H prefix is used.</p>
<p>If CPUID.01H:ECX.RDRAND[bit 30] = 0.</p></td></tr></table>
<h2>Real-Address Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p>
<h2>Virtual-8086 Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p>
<h2>Compatibility Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p>
<h2>64-Bit Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p></body></html>